1. Field of the Invention
The invention relates to layers in substrate wafers as set forth in the classifying portion of claim 1.
2. Description of Related Art
Advantages in terms of power consumption, signal processing speed and production costs are to be expected in relation to previously known multi-chip structures if for example highly integrated processor circuits (digital circuitry technology) can be integrated with high-frequency circuits for transmitting and receiving components (analog circuitry technology) on a chip.
Such a combination of various circuit components of a digital and analog nature on a chip places high demands on technologists, component engineers and circuit developers. This results from the fact that the individual technology processes and component constructions are based on optimisation criteria which in part are in conflict or difficult to reconcile and in addition joint operation of the circuits on one chip can give rise to unwanted interactions.
Highly doped p+-substrate wafers with a p−-doped epilayer are typically used for the production of heavily scaled digital circuits in order to ensure a sufficient safeguard against the occurrence of latch-up, the thyristor-like firing of a four-layer arrangement as occurs for example in the case of CMOS-inverters, which is damaging in terms of the circuit function.
In contrast, the use of substrate wafers which are of as high resistance as possible is advantageous for high-frequency circuits in order to keep down currents which are capacitively or inductively coupled into the substrate, as they result in an increased power consumption, a reduction in quality in coils or so-called substrate noise. At the same time the influence of interference signals, for example from the digital circuits, on sensitive analog circuits, is reduced.
There are various approaches for simultaneously satisfying the various demands on the substrate properties in the combination of digital and analog high-frequency circuits on a chip. Thus A. Monroy et al, BCTM 1999, 7.3, involves the production of n+- and p+-regions which are buried by epitaxy and which are structured by means of an implantation mask on a p−-substrate, in order to ensure both latch-up resistance by virtue of highly doped well regions and also low high-frequency losses by virtue of a high-resistance substrate. That procedure however gives rise to both additional costs due to additional process steps of structuring, well production and epitaxy and also limitations in regard to the design of minimal n- and p-well regions. Those limitations result from lateral displacement of the buried n+ (p+)-regions with respect to the n- and p-wells of the CMOS technology by virtue of mask maladjustment or by virtue of the lateral spread of the buried n+ (p+)-regions during deep diffusion.
The proposal by M. R. Frei et al, IEDM 1999, page 757, in which a buried p+-layer is epitaxially introduced instead of the p+-substrate, does admittedly circumvent the above-indicated difficulties, but it includes unsatisfactory compromises in regard to latch-up resistance or high-frequency substrate losses. The compromises follow in terms of latch-up resistance from the substrate resistance which is substantially increased with respect to a p+-substrate while in terms of the high-frequency substrate losses the compromises arise out of the markedly lower level of substrate resistance and higher capacitances between n-wells and substrate in comparison with a p−-substrate.
In order to effectively increase the latch-up resistance without a p+-substrate or without highly conductive, epitaxially buried n+/p+-layers, it is necessary to improve the conductivity of the n- and p-wells.
R. Mahnkopf et al, JEDM 1999, page 849, reports that, in the case described there, even when foregoing a p+-substrate, latch-up can be sufficiently suppressed if an additional masked boron implant is used. The arrangement described therein however does not include any proposal in terms of resolving the problem of shielding interference signals from nMOS-transistors by means of suitable doping profiles, as is achieved with A. Monroy et al, BCTM 1999, 7.3, by virtue of epitaxially buried n+-regions which are contacted laterally by way of a collector shaft. In order to save on process expenditure and in order not to lose the scaling of highly integrated CMOS-circuits, which is achieved with a p+-substrate, production of that transistor structure by implantation would be advantageous.
In that respect buried dopant profiles with the highest possible dose and steepness are to be aimed at. In regard to suitable implantation doses for so-called retrograde wells, consideration is to be given to various criteria as, because of latch-up resistance, layer resistances which are as low as possible are required, but levels of concentration which are sufficiently low, in relation to surface area, are necessary in order to ensure low source-drain capacitances and to be able to adjust the threshold voltage of the MOS-transistors independently of the retrograde well doping. In addition the possible dose range is limited, in accordance with the previous known state of the art, see for example K K Bourdelle, J Appl Phys, Vol 86, page 1221, 1999, as, in dependence on the kind of ion, in a given dose range which is preferably of interest for the production of retrograde wells, it is not possible for implantation damage to be defect-free restored.
H. J. Gossmann et al, IEDM 1998, page 725, produce a buried carbon layer by implantation in order to attenuate the reverse ‘short-channel effect’ in MOS-transistors. For the carbon doses required for that purpose however it is found that, in spite of positioning the maximum of the implantation profile in deeper zones which are not depleted in respect of mobile charge carriers, the source/drain diodes exhibit markedly increased leakage currents, whereby the use thereof in highly integrated circuits is in doubt.
Bogen et al, Proceedings of the 11th International Conference on Ion Implantation Technology, 1996, page 792, intend using the buried carbon layers produced by means of high-energy implantation for a reduction in the life and thus the diffusion length of minority carriers and finally for an increase in latch-up resistance. Because of the excessive depth of the layer introduced (>3 μm) however in the case of a typical current path, in the event of latch-up triggering, the desired effect would fail to occur unless, as also established by Gossmann et al, IEDM 1998, page 725, the lives were considerably reduced in the regions above the buried carbon layer. That reduction however is absolutely to be avoided as slight leakage currents are required in the space charge zones between source-drain regions and wells, but also at the n-well/p-substrate transition. The variants presented hitherto do not provide any way of satisfying that demand.